NXP Semiconductors /LPC176x5x /CCAN /TXSR

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Interpret as TXSR

Description

CAN Central Transmit Status Register

Fields

TS1	When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).
TS2	When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)
RESERVED	Reserved, the value read from a reserved bit is not defined.
TBS1	When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR).
TBS2	When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR).
RESERVED	Reserved, the value read from a reserved bit is not defined.
TCS1	When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR).
TCS2	When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR).
RESERVED	Reserved, the value read from a reserved bit is not defined.

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